Phase-locked loop (PLL) based frequency synthesizers are widely utilized in radio frequency (RF) communication devices, such as an RF transmitter. The PLL based frequency synthesizer normally includes a phase detector, a local oscillator (LO), and a frequency divider. An output signal provided by the LO is fed through the frequency divider back to the phase detector to be compared to a reference signal. Once the output signal of the LO is locked with the reference signal in phase and frequency, the frequency synthesizer is settled.
Alternatively, frequency synthesizers may be built using a frequency locked loop (FLL), which includes a frequency detector, an LO, and a frequency divider. An output signal provided by the LO is fed through the frequency divider back to the frequency detector to be compared to a reference signal. Once the output signal of the LO is locked with the reference signal in frequency (may or may not be in phase), the frequency synthesizer is settled. Since the FLL based frequency synthesizers only require a frequency lock, the FLL based frequency synthesizers may have a shorter settle time compared to the PLL based frequency synthesizers. Further, if the frequency difference between the output signal and the reference signal is higher than a certain level, the PLL based frequency synthesizers may fail to settle.
Typically, the frequency of the output signal of the LO is at a GHz-level, thus the frequency divider, which is used to reduce the frequency of the output signal of the LO in the feedback loop, requires a GHz-level clock. In addition, if the frequency of the reference signal is much lower than the frequency of the output signal of the LO, the frequency divider will be a high-power consumption component.
Accordingly, there remains a need for an improved frequency synthesizer design, which is able to utilize the fast settle time of the FLL and reduce the power consumption of the final product without introducing significant noise in the output signal.